PCB calculators: trace width, impedance, via current and MSL
Four quick checks for layout and production, with the formula and the limits of each one shown next to the result.
Runs in your browser. Nothing you enter is sent anywhere.
Trace width vs current (IPC-2152)
Minimum trace width for a current and an allowed temperature rise, for outer and inner layers.
How it is calculated and its limits
IPC-2152 replaced the old IPC-2221 charts in 2009. It gives no single formula, so this calculator uses a widely published curve fit of the IPC-2152 baseline chart:
A [mil²] = (117.555 · ΔT^-0.913 + 1.15) · I^(0.84 · ΔT^-0.018 + 1.159)
width = A / copper thickness
The baseline chart is for a trace in a 1.78 mm FR-4 board without copper planes, in still air. It is conservative for most real boards: copper planes, a thinner dielectric to a plane and airflow all let the trace carry more current. IPC-2152 uses the same baseline for external traces, which in practice run a little cooler.
For comparison the legacy IPC-2221 result is shown for the selected layer:
I = k · ΔT^0.44 · A^0.725 k = 0.048 external, 0.024 internal
Use it for currents up to about 30 A and temperature rises of 1 to 100 °C. Resistance uses copper at 1.724 µΩ·cm (20 °C) and 0.393 %/°C, evaluated at ambient plus the temperature rise. Long high-current traces, pulsed loads and traces next to hot components need a thermal simulation or a measurement.
Controlled impedance: microstrip and stripline
Characteristic impedance of a single-ended trace, and the width that gives a target impedance.
How it is calculated and its limits
These are the closed-form approximations of IPC-2141, with t the copper thickness:
microstrip: Z0 = 87 / √(εr + 1.41) · ln(5.98 h / (0.8 w + t)) valid 0.1 ≤ w/h ≤ 2, 1 ≤ εr ≤ 15
stripline: Z0 = 60 / √εr · ln(4 b / (0.67 π (0.8 w + t))) valid w/b < 0.35, t/b < 0.25
delay: microstrip 85 · √(0.475 εr + 0.67) ps/in, stripline 85 · √εr ps/in
For stripline, b is the distance between the two reference planes with the trace centred between them. Inside their validity range the formulas are typically within a few ohms of a field solver; outside it they can be badly wrong, and the target width is then not given.
They ignore solder mask, the trapezoidal etch profile, glass weave and the frequency dependence of εr, and they do not cover differential pairs. Use the result for stack-up planning, then let the board fabricator confirm the final width with its field solver and its own laminate data. Comtec Labs builds controlled-impedance boards with partner fabs.
Via current capacity
Current a plated through-hole via carries for a temperature rise, with its resistance and voltage drop.
How it is calculated and its limits
The plated barrel is treated as a conductor with the cross-section of a copper tube, using the same IPC-2152 curve fit as the trace calculator:
A = π · t · (d + t) d = finished hole, t = plating
I = (A / (117.555 · ΔT^-0.913 + 1.15))^(1 / (0.84 · ΔT^-0.018 + 1.159))
A via is short and usually connects to planes that spread its heat, so the real capacity is often higher than this. The figures do not cover filled or capped vias, microvias or pulsed currents. Several vias in parallel share the current only if their paths are equal; place them evenly and add margin.
MSL floor life and baking (J-STD-033)
How long a moisture-sensitive component may stay out of its dry pack, what is left, and the reference bake when it is exceeded.
How it is calculated and its limits
Floor life is the time a moisture-sensitive component may spend outside its dry pack before reflow. J-STD-033 gives it at the reference conditions of ≤ 30 °C and 60 %RH (MSL 1: ≤ 30 °C / 85 %RH): MSL 1 unlimited, MSL 2 one year, MSL 2a four weeks, MSL 3 168 h, MSL 4 72 h, MSL 5 48 h, MSL 5a 24 h. MSL 6 parts must be baked before use and reflowed within the time on the label.
Above the reference conditions the floor life is shorter and this calculator does not give a figure: use the derating tables of J-STD-033 or treat the parts as exceeded. Below them the standard value is a safe, conservative figure.
The bake times are the reference values of J-STD-033 Table 4-1 for parts whose floor life has been exceeded by more than 72 hours, by package body thickness up to 4.5 mm. Reels and many trays do not tolerate 125 °C. Always check the current revision of the standard and the component label, which take precedence. At Comtec Labs moisture-sensitive devices are kept in dry storage, baked when needed and their floor life is recorded.
Planning a board? Send the Gerbers and BOM with a quote request and we review manufacturability with the quote.
Request a quote